1. Field of the Invention
The present invention-relates generally to an etching process for forming a trench of the semiconductor, and in particular to an etching process for forming a contact window or a via hole with high aspect ratio.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductor devices, become highly integrated the area occupied by the device shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks to the deep sub-micron region, some problems described below are incurred due to the scaling down process.
Dynamic random access memory (DRAM) is applied broadly in the field of integrated circuits devices, and more importantly, in the electronics industry. These devices provide a means of temporary data storage, and they are used in many digital systems, such as computers. Dynamic random access memory (DRAM) with higher capacitance is necessary for the development of the industry. As a result, dynamic random access memory with higher density and capacitance are of great interest and are developed by the related industry. Because intense competition in the Dynamic random access memory (DRAM) marketplace, it is essential that manufacturers reduce the cost of their Dynamic random access memory (DRAM) circuits. To reduce costs and to meet customer expectations for decreasing access times and increasing IC memory size, manufacturers must continually reduce the size of features on the integrated circuit wafer. Such reductions in feature size have brought about much advancement in the art. However, the small geometry presents problems in the predictable manufacture of Dynamic random access memory (DRAM) circuits. How to keep the quality as the size of the device is reduced is now a task for the industry to overcome.
When semiconductor devices of integrated circuit (IC) become highly integrated, the surface of the chips can be not supplied with enough area to make the interconnects. For matching the requirement of interconnects increase when Complementary Metal Oxide Semiconductor (CMOS) devices shrinks, many designs of the integrated circuit have to use dual damascene method. Moreover, it is using the three-dimensional structure of multi-level interconnects at present in the deep sub-micron region, and inter-metal dielectric (IMD) as the dielectric material which is used to separate from each of the interconnects. A conducting wire which connects between the upper and the lower metal layers is called the via plug in semiconductor industry. In general, if an opening which forms in the dielectric layer exposure to devices of the substrate in the interconnects, is called a via. Therefore, the upper and he lower metal layers are electrically connected each other by way of the metal plug in the connect hole or via hole.
In general, in the stacked structure of the dynamic random access memory (DRAM), there is a plurality of dielectric layers 110 with multi-levels on the semiconductor substrate 100, a plurality of gates 120 are individually located in the plurality of dielectric layers 110 with multi-levels, a plurality of contact windows 130 are individually located on the plurality of gates 120, and a plurality of via holes 140 are located on the semiconductor substrate 100, as shown in FIG. 1A. Because of the levels where the plurality of dielectric layers 110 are formed are different, the deepness for forming the plurality of contact windows 130 are different from each other, and the deepness for forming the plurality of via holes 140 are more deeper. In the semiconductor process, the ratio (H/W) of the trench width and the trench deepness is called xe2x80x9cAspect Ratioxe2x80x9d. If the aspect ratio is raised, the trench deepness will be increased or the trench width will be decreased, so that the etching process for forming the trench will be more difficult. For the deep sub-micron technology, the design rule has been scaling down, so that the devices must have the contact windows or via holes with high aspect ratio. Especially, in the dynamic random access memory (DRAM) etching process for forming the contact windows or via holes with high aspect ratio are hard to perform. Furthermore, when the aspect ratio of the contact windows is smaller and smaller, the etching capability of the via holes with high aspect ratio is very important below the process of the dynamic random access memory.
In the conventional etching process, the etchant for etching the trench with a high aspect ratio usually uses two kinds of etching recipes that are C4F8/O2/Ar/CO. Nevertheless, the etching process is terminated during the etching process when forming the trench with a high aspect ratio due to the above etchant with an etching capability that is not enough, so the deepness of the trench has yet to be achieved. This is, the xe2x80x9cetching stopxe2x80x9d effect, as shown in FIG. 1B. Especially, when the aspect ratio of the trench is more than 10, the etching stop effect will be more serious. Moreover, the traditional etchant has higher etching selectivity between different dielectric layers 110, such as oxide/nitride, so the process environment has to be changed to etch through the different dielectric layers 110, and hence, waste of process cycle time. On the other hand, the traditional etchant has lower etching selectivity to photoresist layer 150, so that the remainder of the photoresist layer 150 is not enough after the etching process. Hence, loss of the photoresist layer 150 causes the predetermined width of the trench to get out of control, so that the critical dimension of the trench can not be controlled, for example, maybe the predetermined width of the trench becomes more wider, as shown in FIG. 1C. Although the photoresist layer 150 will be lost during the etching process, still a portion of photoresist layer 150 will remain on the dielectric layer 110, this issue will always cause a fence of the dielectric layer 110 near the trench, as shown in FIG. 1D. For the dynamic random access memory (DRAM) with gates that are located on multi-levels, the contact windows and via holes with different aspect ratios are difficult to form by way of using an etching process with one time and traditional etchant. Conventional etching process makes the performance, quality and yield of the devices to worsen, and the process cycle time also increases, hence, additional cost. In accordance with the above description, a new and improved etching method for forming trench is therefore necessary so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a method is provided for forming a trench with a high aspect ratio that substantially overcomes the drawbacks of the above mentioned problems that arise from conventional methods.
Accordingly, it is a main object of the present invention to provide an etching process for forming a trench with a high aspect ratio. This invention can utilize the new etching recipe to perform an etching process one time, so as to form the contact windows and the via holes having different aspect ratios and simplify the process step to reduce the process cycle time. Furthermore, the etching capability of the etchant in this invention is very strong to prevent the etching stop effect, so as to form the semiconductor device with a small critical dimension. Therefore, this invention is appropriate for deep sub-micron technology.
Another object of the present invention is to provide a method for forming the contact windows and the via holes with different aspect ratios. The present invention can utilize a new etching recipe to raise the etching selectivity between the dielectric layer and the photoresist layer and reduce the etching selectivity between the dielectric layers from each other, so as to avoid losing the photoresist layer and punch through the dielectric layers at one time, whereby the critical dimension of the trench can be kept and the profile of the trench is more vertical, further, forming the fences of the dielectric can also be prevented. Moreover, the etchant of the present invention utilizes the mixing gas that comprises a C4F6 or CH2F2 or CF4 or C2F6 to raise the etching selectivity between the dielectric layer and the photoresist layer to about 15 and reduce the etching selectivity between the dielectric layers from each other to about 1. Therefore, the present invention provides cost reduction, performance, quality and yield additions to the device. Hence, this invention corresponds to economic effect and utilization in industry.
In accordance with the present invention, a new etching process for forming a trench with high aspect ratio is disclosed. First of all, a semiconductor substrate is provided, the semiconductor substrate has a dielectric layer thereon. Then a photoresist layer is formed and defined on the dielectric layer. Next, an etching process is performed by the photoresist layer as an etched mask to form a trench in the dielectric layer, wherein the etchant of the etching process comprises a mixing gas with a C4F6 gas or a CH2F2 gas, such as C4F6/CH2F2/Ar/O2 or C4F6/CH2F2/Ar/O2/CF4 or C4F6/CH2F2/Ar/O2/C2F6, accordingly, the etching capability of the etchant and the etching selectivity between the dielectric layer and the photoresist layer can be raised. Finally, the photoresist layer is removed to form the contact window or the via hole with high accurate critical dimension.